Introduction to digital design, Verilog coding, RTL verification, synthesis, gate-level verification, STA, floorplanning, placement, CTS, routing, and verification with Calibre.
Learning Outcome
- Gain foundational knowledge of digital design principles and workflows
- Develop skills in coding digital circuits using Verilog
- Learn how to verify circuit functionality at both the Register Transfer Level (RTL) and gate level
- Convert high-level Verilog designs into hardware-ready formats
- Analyse and optimise circuit timing for accurate performance
- Gain proficiency in floorplanning, placement, clock tree synthesis, and routing of digital circuits
- Use Calibre by Mentor Graphics to ensure design accuracy
Methodology
This course will be conducted in a workshop fashion, whereby the basic theory and concepts will be presented, followed by hands-on practice and exercises.
Pre-requisite
- Basic knowledge of electronic circuits and semiconductor devices
- Familiarity with analog design principles
Duration
2 Days
Target Group (who should attend)
- Electrical and electronic engineering students
- Practising engineers and professionals in the semiconductor industry
- Researchers and academicians interested in analog IC design
Day 1
- Brief Introduction to Digital Design
- Writing a Verilog Code
- RTL Verification
- Synthesis
- Gate-level Verification
Day 2
- Static Timing Analysis
- Floorplan
- Placement
- Clock Tree Synthesis
- Routing
- Verification using Caliber by Mentor Graphics
